The Crucial Advantage



Crucial IP’s VPC-1 deinterlacer has exceptional image quality and is near the limit of what’s possible with motion adaptive class solutions. Our VPC-1 deinterlacer, VSC-1 scaler and other IP cores are in-use today by leading broadcast manufacturers.

The Research and Development team at Crucial IP have decades of experience developing image processing products for commercial IC providers including Genesis Microchip, Pixelworks and others. We have intimate knowledge of the issues involved in designing high quality deinterlacing, scaling and other algorithms. Our algorithms have been honed through hundreds of hours of subjective and objective testing.

The following table summarizes key performance areas of Crucial IP’s VPC-1 deinterlacer and VSC-1 scaler IP cores compared against industry standard solutions. Included in the comparison are the two most popular ASSP solutions as well as two popular FPGA based solutions. Performance categories include low angle detection, noise immunity and low motion stability, immunity to motion aliasing (fast or repetitive motion) and robustness of the cadence detection system. In summary, Crucial IP vastly out-performs the two FPGA based solutions and is equal or better in every aspect to the two ASSPs.

Low Angle Very Good Good Very Good Poor N/A
Noise Immunity Very Good Good Very Good Poor Poor
Motion Aliasing Very Good Good Very Good Poor Poor
Cadence Detection Very Good Good Good Poor N/A

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Low Risk of Adoption

One of the most important factors in mitigating risk is the ability to fully evaluate all aspects of the IP performance prior to purchase. Evaluation happens in real-time, in your lab, at your leisure, using source material that you consider important. Crucial IP’s demonstration systems are available on popular development kits from both Xilinx and Altera. If you already have a supported kit, we can simply send you an FPGA programming bitstream. If you don’t have a kit, we can help in setting you up. The ability to evaluate our IP prior to purchase completely eliminates any risk associated with in-house development. In-house development is enormously risky with a very real chance that after many man-months or man-years of effort, there may be nothing of value to show for it. Indeed, several of our customers attempted and later abandoned in-house development before selecting one of our solutions. The signal interface and programming model for any of our IP cores may be reviewed prior to purchase. This helps in assessing the effort required to integrate our IP into your system. The code and firmware for the entire demo system is provided with the IP purchase which, along with our product documentation, may be used as a reference for developing your system. All of our intellectual property cores are subjected to continuous randomized testing with checking against a golden C-model. The code has been run through hundreds of thousands of unique tests, stressing all combinations of data valid and data stalling patterns, all combinations of data values, and so on. It is extremely unlikely that your implementation will reveal some strange corner case flaw with the design. However, that said, our standard support agreement specifies that any interface related issue that is uncovered will be resolved without cost and without consuming contractual support hours. Each purchase includes a specified number of hours of expert technical support to aid with integration issues. Source code is available to those who opt for our source code license agreement. This can provide peace of mind and ensures that the code may be ported to any FPGA. All IP products are also available in encrypted form at lower cost (tied to FPGA vendor tools). Even with this option, the code may still be ported to any FPGA family or device from the selected manufacturer.


The costs of Crucial IP products range from a few months to a year’s worth of salary for a single engineer, for a full source code, royalty free, perpetual-use license. Royalty based licensing is also available for encrypted code with substantially lower up front NRE. In-house development costs of similar IP would be far greater. Even seemingly low value “textbook” IP such as scaling may be fraught with subtleties such as edge handling, 422 sub-sampling, coefficient generation and filter bandwidth etc. Even implementation details like parameterized pixel size with proper saturation handling can be tricky. Complex IP such as motion adaptive deinterlacing and MPEG artifact reduction can take years to develop. The option of in-house development raises the issue of opportunity cost. While developing IP which is already available, what opportunities for your company are you missing?


All IP cores can be tailored at build-time using the provided Verilog parameters. Most attributes have been parameterized wherever it’s useful to do so, including such things as data width, number of channels, number of taps, coefficient precision and line length, to name just a few. In addition, the CXC-1 (Configurable Cross-Converter) and CMV-1 (Configurable Multi-Viewer) are themselves parameterized integrations of other IP cores. Crucial IP cores can be easily integrated with other customer or 3rd party IP. Available wrappers provide direct compatibility with Altera’s system integration tool – Qsys.